A variety of battery powered portable devices, such as mobile phones, notebook computers and the like, have become popular. Each portable device may employ a plurality of integrated circuits. Each integrated circuit may comprise a large number of transistors. During an active mode, the change of logic state causes a plurality of charge and discharge processes across the gate of a transistor and corresponding change in the voltage across the output parasitic capacitor of the transistor. An amount of energy dissipated during the logic state change described above is unavoidable because of the physical characteristics of a transistor. On the other hand, leakage current is a major power loss when an integrated circuit is in an idle mode. The leakage current of an integrated circuit may result from a variety of reasons. However, a good design can reduce leakage current power consumption so as to extend battery life.
Electronic devices such as a computer may be powered up in accordance with a specific power up sequence. For example, a computer's peripheral devices may be powered up earlier than its core device. The early ramp-up of the peripheral devices may cause a logic state wherein the high voltage for the peripheral devices is on and the low voltage for the core device is off. Alternatively, when the computer enters a power saving mode, the system management unit of the computer may shut down some low voltage rails so as to save power consumption. Under either situation, some logic devices are not set to a fixed logic state. As a result, leakage current may be induced accordingly.
Furthermore, other factors may contribute to leakage current in integrated circuits. A direct path between an N-type Metal Oxide Semiconductor (NMOS) transistor and a P-type Metal Oxide Semiconductor (PMOS) transistor connected in series is a major source of leakage current. For example, in an integrated circuit having two voltage levels. That is, a high voltage level (e.g., 3.3V) is used to power Input/Output (I/O) devices. A low voltage level (e.g., 1.2V) is used to power a core device such as a central processing unit (CPU). The mismatch between two voltage levels may cause a logic error. More particularly, an I/O buffer having an NMOS transistor and a PMOS transistor in series may receive an inadequate gate drive voltage signal from the output of a core device. Such an inadequate gate drive voltage signal causes an uncertain logic for transistors operating under high voltage level, the lower voltage from the output of a core device which partially turns on the NMOS transistor and partially turns off the PMOS transistor due to its inadequate voltage level. The simultaneous conduction of both the NMOS transistor and the PMOS transistor results in a large amount of leakage current. Such a large amount of leakage current may increase power consumption. Consequently, the battery life of a portable device may be significantly reduced.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.